Intel opens the era of trillion transistors for AI chips

At the recent IEEE Packaging Technology Conference, Intel redefined the boundaries of chip packaging with three breakthrough technologies: 3D structure EMIB-T interconnect, low thermal gradient hot pressing bonding process, and modular heat sink structure. Together, they pushed the integration area of single-chip packaging to exceed 10,000 square millimeters, paving the way for the large-scale and high-performance of AI chips. This technological innovation not only marks the leap from 2D to 3D packaging technology, but also indicates that AI computing power is about to enter a new era of "trillion transistors".

The traditional 2.5D packaging technology is limited by the planar interconnection method of silicon bridges and substrates, making it difficult to meet the high bandwidth and low latency requirements of AI chips. Intel's EMIB-T (Embedded Multi-Die Interconnect Bridge with TSV) achieves vertical penetration of signals and power by embedding through-silicon vias (TSVs) in the silicon bridge. Compared to traditional EMIB, the interconnection density of EMIB-T is increased by 10 times, and the data transmission rate supports ultra-high bandwidth interfaces such as HBM4, while reducing the power transmission resistance by 30%, significantly reducing signal noise and power consumption. This technological breakthrough makes it possible to integrate CPU, GPU, IO chips and high bandwidth memory in a single chip package. For example, in AI training chips, EMIB-T can support up to 24 HBM memory stacks with a memory bandwidth exceeding 10TB/s.

As the size of chip packaging expands, the warping problem caused by thermal expansion has become a key bottleneck restricting yield. Intel's low thermal gradient hot press bonding process compresses the thermal expansion difference between the chip and the substrate to the micrometer level by precisely controlling the temperature gradient during the bonding process. This process triggers a dual control mechanism of pressure and position at the moment of bonding, ensuring the bonding accuracy of each pair of bumps. The measured data shows that this technology increases the yield of large packages with a size of more than 450mm² by 25%, while supporting the reduction of bump spacing from 45 microns to 25 microns, leaving room for future improvement in packaging integration.

The ultra-high computing power demand of AI chips has led to a sharp increase in thermal design power consumption (TDP). Intel's modular heat sink structure optimizes the thermal interface material (TIM) coupling by splitting the plate and reinforcing ribs, reducing solder voids by 25% and improving thermal conductivity efficiency by 40%. More importantly, this design supports an integrated heat sink (IHS) with integrated microchannels, allowing liquid to directly cool the processor core. Tests have shown that this heat sink can stably support chip packaging with TDP up to 1000W, which is three times more efficient than traditional air cooling solutions. In AI inference chips, this technology reduces the temperature of the chip by 20°C and improves performance stability by 15% when it is fully loaded.

The synergistic effect of the three technologies is particularly evident in AI chips. Taking Intel's next-generation AI training chip as an example: EMIB-T achieves 3D stacking of CPU and 8 HBM3E memories, low thermal gradient hot pressing bonding ensures the manufacturing yield of 200 billion transistor chips, and modular heat sinks control the TDP within 800W. This design enables the chip to achieve a 3 times increase in inference speed and a 50% optimization in energy efficiency ratio in ResNet-50 model training compared to the previous generation. AWS and Cisco have announced the application of EMIB-T technology to the next generation of servers, and it is expected to achieve a single server AI computing power breakthrough of 100PFLOPS by 2026.

Intel's breakthrough in packaging technology not only consolidates its leadership position in the field of advanced packaging, but also has a profound impact on the global semiconductor industry chain. On the one hand, the compatibility of EMIB-T and UCIe standards will accelerate the standardization process of the Chiplet ecosystem. It is expected that by 2027, the market share of AI chips based on Chiplet will reach 40%. On the other hand, the open source design concept of modular heat sinks promotes collaborative innovation between heat sink manufacturers and chip manufacturers, driving a 60% reduction in the cost of liquid cooling technology.

In this revolution of packaging technology, Intel has taken the attitude of "transcending Moore's Law" and shifted the focus of chip performance improvement from process technology to system-level integration. With the mass production of EMIB-T packaging in the second half of 2025, the computing power density and energy efficiency ratio of AI chips will usher in a qualitative leap, and the prelude to the era of trillion transistors is being quietly unveiled by innovations in packaging technology.